cpldfit:  version J.40                              Xilinx Inc.
                                  Fitter Report
Design Name: LPTAD                               Date:  2- 8-2010, 10:17PM
Device Used: XC9572XL-10-VQ64
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
29 /72  ( 40%) 25  /360  (  7%) 20 /216 (  9%)   6  /72  (  8%) 28 /52  ( 54%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1           0/18        0/54        0/90       0/13
FB2          16/18       10/54       15/90      12/13
FB3          11/18       10/54       10/90       7/14
FB4           2/18        0/54        0/90       2/12
             -----       -----       -----      -----    
             29/72       20/216      25/360     21/52 

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    7           7    |  I/O              :    25      46
Output        :   21          21    |  GCK/IO           :     0       3
Bidirectional :    0           0    |  GTS/IO           :     2       2
GCK           :    0           0    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     28          28

** Power Data **

There are 29 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld:1007 - Removing unused input(s) 'lpt_autofeed'.  The input(s) are
   unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'lpt_datastrobe'.  The input(s) are
   unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'lpt_init'.  The input(s) are
   unused after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'lpt_selectinput'.  The input(s)
   are unused after optimization. Please verify functionality via simulation.
*************************  Summary of Mapped Logic  ************************

** 21 Outputs **

Signal                                    Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                                      Pts   Inps          No.  Type    Use     Mode Rate State
lpt_data<0>                               0     0     FB2_3   58   I/O     O       STD  FAST 
lpt_data<1>                               0     0     FB2_4   59   I/O     O       STD  FAST 
lpt_data<2>                               0     0     FB2_5   61   I/O     O       STD  FAST 
lpt_data<3>                               0     0     FB2_6   62   I/O     O       STD  FAST 
lpt_data<4>                               0     0     FB2_8   63   I/O     O       STD  FAST 
lpt_data<5>                               0     0     FB2_9   64   GSR/I/O O       STD  FAST 
lpt_data<6>                               0     0     FB2_10  1    I/O     O       STD  FAST 
lpt_data<7>                               0     0     FB2_11  2    GTS/I/O O       STD  FAST 
lpt_ack                                   2     5     FB2_12  4    I/O     O       STD  FAST RESET
lpt_busy                                  2     6     FB2_14  5    GTS/I/O O       STD  FAST RESET
lpt_paperout                              2     6     FB2_15  6    I/O     O       STD  FAST RESET
lpt_select                                2     2     FB2_17  7    I/O     O       STD  FAST RESET
ext_1o                                    1     1     FB3_3   31   I/O     O       STD  FAST 
ext_2o                                    0     0     FB3_4   32   I/O     O       STD  FAST 
ext_3o                                    0     0     FB3_5   24   I/O     O       STD  FAST 
ext_4o                                    0     0     FB3_6   34   I/O     O       STD  FAST 
ext_6o                                    0     0     FB3_11  33   I/O     O       STD  FAST 
ext_7o                                    1     1     FB3_12  40   I/O     O       STD  FAST 
lpt_error                                 0     0     FB3_16  42   I/O     O       STD  FAST 
ext_1x2o                                  0     0     FB4_6   49   I/O     O       STD  FAST 
ext_1x1o                                  0     0     FB4_11  48   I/O     O       STD  FAST 

** 8 Buried Nodes **

Signal                                    Total Total Loc     Pwr  Reg Init
Name                                      Pts   Inps          Mode State
Mtrien_ext_1o/Mtrien_ext_1o_RSTF__$INT    1     3     FB2_7   STD  
lpt_paperout_OBUF/lpt_paperout_OBUF_RSTF  2     5     FB2_13  STD  
lpt_busy_OBUF/lpt_busy_OBUF_RSTF          2     5     FB2_16  STD  
Mtrien_ext_7o/Mtrien_ext_7o_RSTF__$INT    2     4     FB2_18  STD  
lpt_select_OBUF/lpt_select_OBUF_SETF      2     6     FB3_14  STD  
lpt_select_OBUF/lpt_select_OBUF_RSTF      2     6     FB3_15  STD  
Mtrien_ext_7o                             2     5     FB3_17  STD  RESET
Mtrien_ext_1o                             2     5     FB3_18  STD  RESET

** 7 Inputs **

Signal                                    Loc     Pin  Pin     Pin     
Name                                              No.  Type    Use     
stat<3>                                   FB1_2   8    I/O     I
stat<2>                                   FB1_5   9    I/O     I
stat<0>                                   FB1_6   10   I/O     I
stat<1>                                   FB1_8   11   I/O     I
ext_5i                                    FB3_10  39   I/O     I
ext_1x4i                                  FB4_3   46   I/O     I
ext_1x3i                                  FB4_4   47   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
(unused)              0       0     0   5     FB1_2   8     I/O     I
(unused)              0       0     0   5     FB1_3   12    I/O     
(unused)              0       0     0   5     FB1_4   13    I/O     
(unused)              0       0     0   5     FB1_5   9     I/O     I
(unused)              0       0     0   5     FB1_6   10    I/O     I
(unused)              0       0     0   5     FB1_7         (b)     
(unused)              0       0     0   5     FB1_8   11    I/O     I
(unused)              0       0     0   5     FB1_9   15    GCK/I/O 
(unused)              0       0     0   5     FB1_10  18    I/O     
(unused)              0       0     0   5     FB1_11  16    GCK/I/O 
(unused)              0       0     0   5     FB1_12  23    I/O     
(unused)              0       0     0   5     FB1_13        (b)     
(unused)              0       0     0   5     FB1_14  17    GCK/I/O 
(unused)              0       0     0   5     FB1_15  19    I/O     
(unused)              0       0     0   5     FB1_16        (b)     
(unused)              0       0     0   5     FB1_17  20    I/O     
(unused)              0       0     0   5     FB1_18        (b)     
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               10/44
Number of signals used by logic mapping into function block:  10
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1         (b)     
(unused)              0       0     0   5     FB2_2   60    I/O     
lpt_data<0>           0       0     0   5     FB2_3   58    I/O     O
lpt_data<1>           0       0     0   5     FB2_4   59    I/O     O
lpt_data<2>           0       0     0   5     FB2_5   61    I/O     O
lpt_data<3>           0       0     0   5     FB2_6   62    I/O     O
Mtrien_ext_1o/Mtrien_ext_1o_RSTF__$INT
                      1       0     0   4     FB2_7         (b)     (b)
lpt_data<4>           0       0     0   5     FB2_8   63    I/O     O
lpt_data<5>           0       0     0   5     FB2_9   64    GSR/I/O O
lpt_data<6>           0       0     0   5     FB2_10  1     I/O     O
lpt_data<7>           0       0     0   5     FB2_11  2     GTS/I/O O
lpt_ack               2       0     0   3     FB2_12  4     I/O     O
lpt_paperout_OBUF/lpt_paperout_OBUF_RSTF
                      2       0     0   3     FB2_13        (b)     (b)
lpt_busy              2       0     0   3     FB2_14  5     GTS/I/O O
lpt_paperout          2       0     0   3     FB2_15  6     I/O     O
lpt_busy_OBUF/lpt_busy_OBUF_RSTF
                      2       0     0   3     FB2_16        (b)     (b)
lpt_select            2       0     0   3     FB2_17  7     I/O     O
Mtrien_ext_7o/Mtrien_ext_7o_RSTF__$INT
                      2       0     0   3     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: ext_1x3i                                   5: lpt_select_OBUF/lpt_select_OBUF_RSTF   8: stat<1> 
  2: ext_5i                                     6: lpt_select_OBUF/lpt_select_OBUF_SETF   9: stat<2> 
  3: lpt_busy_OBUF/lpt_busy_OBUF_RSTF           7: stat<0>                               10: stat<3> 
  4: lpt_paperout_OBUF/lpt_paperout_OBUF_RSTF 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
lpt_data<0>          ........................................ 0
lpt_data<1>          ........................................ 0
lpt_data<2>          ........................................ 0
lpt_data<3>          ........................................ 0
Mtrien_ext_1o/Mtrien_ext_1o_RSTF__$INT 
                     ......X.XX.............................. 3
lpt_data<4>          ........................................ 0
lpt_data<5>          ........................................ 0
lpt_data<6>          ........................................ 0
lpt_data<7>          ........................................ 0
lpt_ack              .X....XXXX.............................. 5
lpt_paperout_OBUF/lpt_paperout_OBUF_RSTF 
                     X.....XXXX.............................. 5
lpt_busy             .XX...XXXX.............................. 6
lpt_paperout         X..X..XXXX.............................. 6
lpt_busy_OBUF/lpt_busy_OBUF_RSTF 
                     .X....XXXX.............................. 5
lpt_select           ....XX.................................. 2
Mtrien_ext_7o/Mtrien_ext_7o_RSTF__$INT 
                     ......XXXX.............................. 4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               10/44
Number of signals used by logic mapping into function block:  10
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1         (b)     
(unused)              0       0     0   5     FB3_2   22    I/O     
ext_1o                1       0     0   4     FB3_3   31    I/O     O
ext_2o                0       0     0   5     FB3_4   32    I/O     O
ext_3o                0       0     0   5     FB3_5   24    I/O     O
ext_4o                0       0     0   5     FB3_6   34    I/O     O
(unused)              0       0     0   5     FB3_7         (b)     
(unused)              0       0     0   5     FB3_8   25    I/O     
(unused)              0       0     0   5     FB3_9   27    I/O     
(unused)              0       0     0   5     FB3_10  39    I/O     I
ext_6o                0       0     0   5     FB3_11  33    I/O     O
ext_7o                1       0     0   4     FB3_12  40    I/O     O
(unused)              0       0     0   5     FB3_13        (b)     
lpt_select_OBUF/lpt_select_OBUF_SETF
                      2       0     0   3     FB3_14  35    I/O     (b)
lpt_select_OBUF/lpt_select_OBUF_RSTF
                      2       0     0   3     FB3_15  36    I/O     (b)
lpt_error             0       0     0   5     FB3_16  42    I/O     O
Mtrien_ext_7o         2       0     0   3     FB3_17  38    I/O     (b)
Mtrien_ext_1o         2       0     0   3     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: Mtrien_ext_1o                            5: ext_1x4i           8: stat<1> 
  2: Mtrien_ext_1o/Mtrien_ext_1o_RSTF__$INT   6: ext_5i             9: stat<2> 
  3: Mtrien_ext_7o                            7: stat<0>           10: stat<3> 
  4: Mtrien_ext_7o/Mtrien_ext_7o_RSTF__$INT 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
ext_1o               X....................................... 1
ext_2o               ........................................ 0
ext_3o               ........................................ 0
ext_4o               ........................................ 0
ext_6o               ........................................ 0
ext_7o               ..X..................................... 1
lpt_select_OBUF/lpt_select_OBUF_SETF 
                     ....XXXXXX.............................. 6
lpt_select_OBUF/lpt_select_OBUF_RSTF 
                     ....XXXXXX.............................. 6
lpt_error            ........................................ 0
Mtrien_ext_7o        ...X..XXXX.............................. 5
Mtrien_ext_1o        .X....XXXX.............................. 5
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
(unused)              0       0     0   5     FB4_2   43    I/O     
(unused)              0       0     0   5     FB4_3   46    I/O     I
(unused)              0       0     0   5     FB4_4   47    I/O     I
(unused)              0       0     0   5     FB4_5   44    I/O     
ext_1x2o              0       0     0   5     FB4_6   49    I/O     O
(unused)              0       0     0   5     FB4_7         (b)     
(unused)              0       0     0   5     FB4_8   45    I/O     
(unused)              0       0     0   5     FB4_9         (b)     
(unused)              0       0     0   5     FB4_10  51    I/O     
ext_1x1o              0       0     0   5     FB4_11  48    I/O     O
(unused)              0       0     0   5     FB4_12  52    I/O     
(unused)              0       0     0   5     FB4_13        (b)     
(unused)              0       0     0   5     FB4_14  50    I/O     
(unused)              0       0     0   5     FB4_15  56    I/O     
(unused)              0       0     0   5     FB4_16        (b)     
(unused)              0       0     0   5     FB4_17  57    I/O     
(unused)              0       0     0   5     FB4_18        (b)     

Signals Used by Logic in Function Block

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
ext_1x2o             ........................................ 0
ext_1x1o             ........................................ 0
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********

FDCPE_Mtrien_ext_1o: FDCPE port map (Mtrien_ext_1o,'0','0',NOT Mtrien_ext_1o/Mtrien_ext_1o_RSTF__$INT,Mtrien_ext_1o_PRE);
Mtrien_ext_1o_PRE <= (stat(0) AND NOT stat(3) AND NOT stat(2) AND NOT stat(1));


Mtrien_ext_1o/Mtrien_ext_1o_RSTF__$INT <= (stat(0) AND NOT stat(3) AND NOT stat(2));

FDCPE_Mtrien_ext_7o: FDCPE port map (Mtrien_ext_7o,'0','0',NOT Mtrien_ext_7o/Mtrien_ext_7o_RSTF__$INT,Mtrien_ext_7o_PRE);
Mtrien_ext_7o_PRE <= (stat(0) AND NOT stat(3) AND NOT stat(2) AND NOT stat(1));


Mtrien_ext_7o/Mtrien_ext_7o_RSTF__$INT <= ((stat(0) AND NOT stat(3) AND NOT stat(2))
	OR (NOT stat(3) AND NOT stat(2) AND stat(1)));


ext_1o_I <= '0';
ext_1o <= ext_1o_I when ext_1o_OE = '1' else 'Z';
ext_1o_OE <= NOT Mtrien_ext_1o;


ext_1x1o <= '0';


ext_1x2o <= '0';


ext_2o <= '0';


ext_3o <= '0';


ext_4o <= '0';


ext_6o <= '0';


ext_7o_I <= '0';
ext_7o <= ext_7o_I when ext_7o_OE = '1' else 'Z';
ext_7o_OE <= NOT Mtrien_ext_7o;

FDCPE_lpt_ack: FDCPE port map (lpt_ack,'0','0',lpt_ack_CLR,lpt_ack_PRE);
lpt_ack_CLR <= (NOT stat(0) AND NOT stat(3) AND NOT stat(2) AND stat(1) AND NOT ext_5i);
lpt_ack_PRE <= (NOT stat(0) AND NOT stat(3) AND NOT stat(2) AND stat(1) AND ext_5i);

FDCPE_lpt_busy: FDCPE port map (lpt_busy,'0','0',lpt_busy_OBUF/lpt_busy_OBUF_RSTF,lpt_busy_PRE);
lpt_busy_PRE <= (stat(0) AND NOT stat(3) AND NOT stat(2) AND NOT stat(1) AND ext_5i);


lpt_busy_OBUF/lpt_busy_OBUF_RSTF <= ((stat(0) AND NOT stat(3) AND NOT stat(2) AND stat(1))
	OR (stat(0) AND NOT stat(3) AND NOT stat(2) AND NOT ext_5i));


lpt_data_I(0) <= '0';
lpt_data(0) <= lpt_data_I(0) when lpt_data_OE(0) = '1' else 'Z';
lpt_data_OE(0) <= '0';


lpt_data_I(1) <= '0';
lpt_data(1) <= lpt_data_I(1) when lpt_data_OE(1) = '1' else 'Z';
lpt_data_OE(1) <= '0';


lpt_data_I(2) <= '0';
lpt_data(2) <= lpt_data_I(2) when lpt_data_OE(2) = '1' else 'Z';
lpt_data_OE(2) <= '0';


lpt_data_I(3) <= '0';
lpt_data(3) <= lpt_data_I(3) when lpt_data_OE(3) = '1' else 'Z';
lpt_data_OE(3) <= '0';


lpt_data_I(4) <= '0';
lpt_data(4) <= lpt_data_I(4) when lpt_data_OE(4) = '1' else 'Z';
lpt_data_OE(4) <= '0';


lpt_data_I(5) <= '0';
lpt_data(5) <= lpt_data_I(5) when lpt_data_OE(5) = '1' else 'Z';
lpt_data_OE(5) <= '0';


lpt_data_I(6) <= '0';
lpt_data(6) <= lpt_data_I(6) when lpt_data_OE(6) = '1' else 'Z';
lpt_data_OE(6) <= '0';


lpt_data_I(7) <= '0';
lpt_data(7) <= lpt_data_I(7) when lpt_data_OE(7) = '1' else 'Z';
lpt_data_OE(7) <= '0';


lpt_error <= '1';

FDCPE_lpt_paperout: FDCPE port map (lpt_paperout,'0','0',lpt_paperout_OBUF/lpt_paperout_OBUF_RSTF,lpt_paperout_PRE);
lpt_paperout_PRE <= (stat(0) AND stat(3) AND NOT stat(2) AND NOT stat(1) AND 
	ext_1x3i);


lpt_paperout_OBUF/lpt_paperout_OBUF_RSTF <= ((stat(0) AND NOT stat(3) AND NOT stat(2) AND stat(1))
	OR (stat(0) AND stat(3) AND NOT stat(2) AND NOT stat(1) AND 
	NOT ext_1x3i));

FDCPE_lpt_select: FDCPE port map (lpt_select,'0','0',lpt_select_OBUF/lpt_select_OBUF_RSTF,lpt_select_OBUF/lpt_select_OBUF_SETF);


lpt_select_OBUF/lpt_select_OBUF_RSTF <= ((stat(0) AND stat(3) AND NOT stat(2) AND NOT stat(1) AND 
	NOT ext_1x4i)
	OR (stat(0) AND NOT stat(3) AND NOT stat(2) AND stat(1) AND NOT ext_5i));


lpt_select_OBUF/lpt_select_OBUF_SETF <= ((stat(0) AND stat(3) AND NOT stat(2) AND NOT stat(1) AND 
	ext_1x4i)
	OR (stat(0) AND NOT stat(3) AND NOT stat(2) AND stat(1) AND ext_5i));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572XL-10-VQ64


   -----------------------------------------------  
  /48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 \
 | 49                                           32 | 
 | 50                                           31 | 
 | 51                                           30 | 
 | 52                                           29 | 
 | 53                                           28 | 
 | 54                                           27 | 
 | 55                                           26 | 
 | 56              XC9572XL-10-VQ64             25 | 
 | 57                                           24 | 
 | 58                                           23 | 
 | 59                                           22 | 
 | 60                                           21 | 
 | 61                                           20 | 
 | 62                                           19 | 
 | 63                                           18 | 
 | 64                                           17 | 
 \ 1  2  3  4  5  6  7  8  9  10 11 12 13 14 15 16 /
   -----------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 lpt_data<6>                      33 ext_6o                        
  2 lpt_data<7>                      34 ext_4o                        
  3 VCC                              35 KPR                           
  4 lpt_ack                          36 KPR                           
  5 lpt_busy                         37 VCC                           
  6 lpt_paperout                     38 KPR                           
  7 lpt_select                       39 ext_5i                        
  8 stat<3>                          40 ext_7o                        
  9 stat<2>                          41 GND                           
 10 stat<0>                          42 lpt_error                     
 11 stat<1>                          43 KPR                           
 12 KPR                              44 KPR                           
 13 KPR                              45 KPR                           
 14 GND                              46 ext_1x4i                      
 15 KPR                              47 ext_1x3i                      
 16 KPR                              48 ext_1x1o                      
 17 KPR                              49 ext_1x2o                      
 18 KPR                              50 KPR                           
 19 KPR                              51 KPR                           
 20 KPR                              52 KPR                           
 21 GND                              53 TDO                           
 22 KPR                              54 GND                           
 23 KPR                              55 VCC                           
 24 ext_3o                           56 KPR                           
 25 KPR                              57 KPR                           
 26 VCC                              58 lpt_data<0>                   
 27 KPR                              59 lpt_data<1>                   
 28 TDI                              60 KPR                           
 29 TMS                              61 lpt_data<2>                   
 30 TCK                              62 lpt_data<3>                   
 31 ext_1o                           63 lpt_data<4>                   
 32 ext_2o                           64 lpt_data<5>                   


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-10-VQ64
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25