Equations

********** Mapped Logic **********
FDCPE_Mtrien_ext_1o: FDCPE port map (Mtrien_ext_1o,'0','0',NOT Mtrien_ext_1o/Mtrien_ext_1o_RSTF__$INT,Mtrien_ext_1o_PRE);
     Mtrien_ext_1o_PRE <= (stat(0) AND NOT stat(3) AND NOT stat(2) AND NOT stat(1));
Mtrien_ext_1o/Mtrien_ext_1o_RSTF__$INT <= (stat(0) AND NOT stat(3) AND NOT stat(2));
FDCPE_Mtrien_ext_7o: FDCPE port map (Mtrien_ext_7o,'0','0',NOT Mtrien_ext_7o/Mtrien_ext_7o_RSTF__$INT,Mtrien_ext_7o_PRE);
     Mtrien_ext_7o_PRE <= (stat(0) AND NOT stat(3) AND NOT stat(2) AND NOT stat(1));
Mtrien_ext_7o/Mtrien_ext_7o_RSTF__$INT <= ((stat(0) AND NOT stat(3) AND NOT stat(2))
      OR (NOT stat(3) AND NOT stat(2) AND stat(1)));
ext_1o_I <= '0';
     ext_1o <= ext_1o_I when ext_1o_OE = '1' else 'Z';
     ext_1o_OE <= NOT Mtrien_ext_1o;
ext_1x1o <= '0';
ext_1x2o <= '0';
ext_2o <= '0';
ext_3o <= '0';
ext_4o <= '0';
ext_6o <= '0';
ext_7o_I <= '0';
     ext_7o <= ext_7o_I when ext_7o_OE = '1' else 'Z';
     ext_7o_OE <= NOT Mtrien_ext_7o;
FDCPE_lpt_ack: FDCPE port map (lpt_ack,'0','0',lpt_ack_CLR,lpt_ack_PRE);
     lpt_ack_CLR <= (NOT stat(0) AND NOT stat(3) AND NOT stat(2) AND stat(1) AND NOT ext_5i);
     lpt_ack_PRE <= (NOT stat(0) AND NOT stat(3) AND NOT stat(2) AND stat(1) AND ext_5i);
FDCPE_lpt_busy: FDCPE port map (lpt_busy,'0','0',lpt_busy_OBUF/lpt_busy_OBUF_RSTF,lpt_busy_PRE);
     lpt_busy_PRE <= (stat(0) AND NOT stat(3) AND NOT stat(2) AND NOT stat(1) AND ext_5i);
lpt_busy_OBUF/lpt_busy_OBUF_RSTF <= ((stat(0) AND NOT stat(3) AND NOT stat(2) AND stat(1))
      OR (stat(0) AND NOT stat(3) AND NOT stat(2) AND NOT ext_5i));
lpt_data_I(0) <= '0';
     lpt_data(0) <= lpt_data_I(0) when lpt_data_OE(0) = '1' else 'Z';
     lpt_data_OE(0) <= '0';
lpt_data_I(1) <= '0';
     lpt_data(1) <= lpt_data_I(1) when lpt_data_OE(1) = '1' else 'Z';
     lpt_data_OE(1) <= '0';
lpt_data_I(2) <= '0';
     lpt_data(2) <= lpt_data_I(2) when lpt_data_OE(2) = '1' else 'Z';
     lpt_data_OE(2) <= '0';
lpt_data_I(3) <= '0';
     lpt_data(3) <= lpt_data_I(3) when lpt_data_OE(3) = '1' else 'Z';
     lpt_data_OE(3) <= '0';
lpt_data_I(4) <= '0';
     lpt_data(4) <= lpt_data_I(4) when lpt_data_OE(4) = '1' else 'Z';
     lpt_data_OE(4) <= '0';
lpt_data_I(5) <= '0';
     lpt_data(5) <= lpt_data_I(5) when lpt_data_OE(5) = '1' else 'Z';
     lpt_data_OE(5) <= '0';
lpt_data_I(6) <= '0';
     lpt_data(6) <= lpt_data_I(6) when lpt_data_OE(6) = '1' else 'Z';
     lpt_data_OE(6) <= '0';
lpt_data_I(7) <= '0';
     lpt_data(7) <= lpt_data_I(7) when lpt_data_OE(7) = '1' else 'Z';
     lpt_data_OE(7) <= '0';
lpt_error <= '1';
FDCPE_lpt_paperout: FDCPE port map (lpt_paperout,'0','0',lpt_paperout_OBUF/lpt_paperout_OBUF_RSTF,lpt_paperout_PRE);
     lpt_paperout_PRE <= (stat(0) AND stat(3) AND NOT stat(2) AND NOT stat(1) AND
      ext_1x3i);
lpt_paperout_OBUF/lpt_paperout_OBUF_RSTF <= ((stat(0) AND NOT stat(3) AND NOT stat(2) AND stat(1))
      OR (stat(0) AND stat(3) AND NOT stat(2) AND NOT stat(1) AND
      NOT ext_1x3i));
FDCPE_lpt_select: FDCPE port map (lpt_select,'0','0',lpt_select_OBUF/lpt_select_OBUF_RSTF,lpt_select_OBUF/lpt_select_OBUF_SETF);
lpt_select_OBUF/lpt_select_OBUF_RSTF <= ((stat(0) AND stat(3) AND NOT stat(2) AND NOT stat(1) AND
      NOT ext_1x4i)
      OR (stat(0) AND NOT stat(3) AND NOT stat(2) AND stat(1) AND NOT ext_5i));
lpt_select_OBUF/lpt_select_OBUF_SETF <= ((stat(0) AND stat(3) AND NOT stat(2) AND NOT stat(1) AND
      ext_1x4i)
      OR (stat(0) AND NOT stat(3) AND NOT stat(2) AND stat(1) AND ext_5i));
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);